RRAM Cell Model
一維導電路徑
Title: Device and SPICE modeling of RRAM devices
Authors: Sheridan, Patrick and Kim, Kuk-Hwan and Gaba, Siddharth and Chang, Ting and Chen, Lin and Lu, Wei
Source: Nanoscale
Year: 2011
Title: A SPICE compact model of metal oxide resistive switching memory with variations
Authors: Guan, Ximeng and Yu, Shimeng and Wong, H-S Philip
Source: IEEE electron device letters
Year: 2012
Title: A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling
Authors: Yu, Shimeng and Gao, Bin and Fang, Zheng and Yu, Hongyu and Kang, Jinfeng and Wong, H-S Philip
Source: 2012 International Electron Devices Meeting
Year: 2012
Title: Verilog-A compact model for oxide-based resistive random access memory (RRAM)
Authors: Jiang, Zizhen and Yu, Shimeng and Wu, Yi and Engel, Jesse H and Guan, Ximeng and Wong, H-S Philip
Source: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
Year: 2014
Notes: modeling the cycle to cycle variation, the source code seems to be problematic
Title: Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design
Authors: Chen, Pai-Yu and Yu, Shimeng
Source: Transactions on Electron Devices
Year: 2015
Notes: the temperature dynamics equation in the source code seems to be problematic
Title: A SPICE model of resistive random access memory for large-scale memory array simulation
Authors: Li, Haitong and Huang, Peng and Gao, Bin and Chen, Bing and Liu, Xiaoyan and Kang, Jinfeng
Source: IEEE Electron Device Letters
Year: 2013
Notes: having the RC models of the cell and the array
Title: Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model
Authors: Li, Haitong and Jiang, Zizhen and Huang, Peng and Wu, Yi and Chen, H-Y and Gao, Bin and Liu, XY and Kang, JF and Wong, H-SP
Source: 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2015
Title: Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model
Authors: Li, Haitong and Jiang, Zizhen and Huang, Peng and Wu, Yi and Chen, H-Y and Gao, Bin and Liu, XY and Kang, JF and Wong, H-SP
Source: 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2015
Notes: having the RC models of the cell and the array
RRAM Array Model
1T1R 陣列
Title: An N40 256Kx44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance
Authors: Chou, Chung-Cheng and Lin, Zheng-Jun and Tseng, Pei-Ling and Li, Chih-Feng and Chang, Chih-Yang and Chen, Wei-Chi and Chih, Yu-Der and Chang, Tsung-Yung Jonathan
Source: 2018 IEEE International Solid-State Circuits Conference-(ISSCC)
Year: 2018
Notes: adopted the common source line architecture
Title: A 40nm 2Mb ReRAM Macro with 85% Reduction in FORMING Time and 99% Reduction in Page-Write Time Using Auto-FORMING and Auto-Write Schemes
Authors: Chiu, Yen-Cheng and Hu, Han-Wen and Lai, Li-Ya and Huang, Tsung-Yuan and Kao, Hui-Yao and Chang, Kuang-Tang and Ho, Mon-Shu and Chou, Chung-Cheng and Chih, Yu-Der and Chang, Tsung-Yung and others
Source: 2019 Symposium on VLSI Technology
Year: 2019
Notes: adopted the common source line architecture
Crossbar 陣列
Title: Modeling and analysis of passive switching crossbar arrays
Authors: Fouda, Mohammed E and Eltawil, Ahmed M and Kurdahi, Fadi
Source: IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2017
Notes: having the RC models of the array
